The inventive concepts relate to a semiconductor device, and more particularly, to a semiconductor device, in which a direct contact and a bit line are formed in a cell array region and a gate electrode structure is formed in a peripheral circuit region, and/or a method of manufacturing the semiconductor device.
As the integration density of a semiconductor device increases, a design rule for elements of the semiconductor device decreases. In addition, in a method of manufacturing a highly integrated semiconductor device, a process of forming a direct contact and a bit line in a cell array region and a process of forming a gate electrode structure in a peripheral circuit region may be performed at the same time. As a process in the cell array region and a process in the peripheral circuit region are performed at the same time, a planarization process such as chemical mechanical polishing (CMP) may be performed in order for the height of the cell array region and the height of the peripheral circuit region to be maintained to be equal to each other.